In the last century, radio transmission of modulated signals has become one of the most widespread means for communication over distance. In recent years, the use of radio communication has become even more ubiquitous with the advent of e.g. wireless local networks and mobile telephones.
A key parameter in radio communication systems is the design of the power amplifiers that amplify radio signals to power levels suitable for transmission by an antenna. The design and performance of the power amplifiers are particularly critical in order to meet system requirements related to adjacent channel interference, low distortion, high power levels, low battery levels etc.
Furthermore, requirements for the functionality of power amplifiers have tended to become more complex over the years. For example, cellular communication systems not only require high performance operation during transmission but also require that the power output level can be varied over a large dynamic range and can be controlled with a high degree of accuracy.
For example, cellular communication systems use power control loops to adjust the transmit power of radio units (both base stations and mobile stations to reflect the current radio propagation conditions. Thus, a transmission from and to a mobile station at the edge of a coverage area and/or in a propagation fade will be at a high power level whereas transmission from and to a mobile station close to the base station will be performed at significantly lower power levels. Accordingly, the radio units comprise functionality for dynamically controlling the output power level of the power amplifiers.
Furthermore, in particular TDMA cellular communication systems, such as the Global System for Mobile communication (GSM), prescribe a tight temporal and frequency domain envelope mask of the transmitted signal. Specifically, as transmission occurs in short bursts, the cellular communication systems prescribe a specific power ramping during power up and power down in order to reduce the spectral spreading of the signal and thereby the adjacent channel interference.
Accordingly, much research has been conducted in the field of optimisation of power amplifiers. One method proposed for controlling the power output level of a power amplifier comprises regulating the output power level by controlling the power supply to the power amplifier.
FIG. 1 illustrates the principle of power supply regulation of the output power level of a power amplifier in accordance with prior art.
In FIG. 1, a power amplifier circuit 101 is operable to amplify a radio signal for transmission via an antenna (not shown). The power amplifier circuit 101 is provided with a power supply having a voltage Vcc which is controlled by a Field Effect Transistor (FET) 103. The FET 103 has a source connected to a battery providing a battery voltage VBat and drain connected to a power supply input of the power amplifier circuit 101.
The power amplifier circuit 101 is coupled such that the output power of the power amplifier depends on the supply voltage Vcc. Thus, for a constant envelope radio signal fed to the power amplifier, the output power of the power amplifier circuit 101 is controlled by the value of the supply voltage Vcc.
The gate of the FET 103 is coupled to an operational amplifier (op-amp) 105 which provides a drive signal that controls the supply voltage Vcc. The supply voltage connection to the power amplifier circuit 101 is fed to the non-inverting input of the op-amp 105 through two resistors 107, 109. The PET 103 is a PMOS FET coupled in an inverting configuration. Thus, the coupling between the op-amp 105, the FET 103 and the two resistors 107, 109 forms a conventional feed-back controlled buffer or amplifier circuit providing high input impedance buffering of the input signal Vin of the op-amp 105 such that Vcc is proportional to Vin. In the example, the resistors 107, 109 of the divider both have a value of R thereby resulting in a gain of the control circuitry of two i.e. in that Vcc=2·Vin.
FIG. 1 furthermore illustrates an example of an input signal 111 which controls the power ramping of the power amplifier circuit 101 in connection with transmission of a burst in a TDMA cellular communication system. Specifically, the specific characteristics of the illustrated power ramping are compatible with the Global System for Mobile communication (GSM).
In accordance with the GSM Technical Specifications, a TDMA burst initiates by an approximately 20 μsec long power up ramp and terminates with an approximately 20 μsec long power down ramp. The power up and down ramp effectively removes higher spectral components from the signal thereby significantly reducing adjacent channel interference. Accordingly, the input signal 111 comprises an approximately 20 μsec long power up ramp component followed by a static component for the duration of the burst, followed by an approximately 20 μsec long power down ramp component. For a mobile station, the signal is then zero until the next transmission burst to the base station.
Thus, the input signal to the op-amp 105 controls the temporal power ramping of the power output level.
Although the circuit of FIG. 1 may meet the requirements of e.g. the GSM system, it has a number of associated disadvantages.
One disadvantage is that the circuit of FIG. 1 requires a supply voltage VBat which is substantially higher than the supply voltage Vcc to the power amplifier circuit 101 in order to guarantee optimal performance. If VBat is not sufficiently large, the FET 103 will enter the linear region of the operating characteristic of the FET. In the linear region, the FET has little gain and effectively operates more as a variable resistor than as a gain element. This significantly alters the dynamic performance of the control loop and results in degraded transient response and substantially increased adjacent channels spurious.
In order to prevent this effect, the circuit of FIG. 1 is conventionally provided with functionality for clamping the power amplifier circuit supply voltage Vcc to a maximum value which ensures that the FET is still operating with a substantial gain. The clamp voltage is determined to comply with the minimum battery voltage in order to ensure that the FET operates with sufficient gain during the entire battery life cycle. Typically, the clamping is performed by limiting the input voltage Vin to a value which ensures full performance at minimum battery voltage. This clamping of the supply voltage Vcc is necessary to avoid the power amplifier distorting the power ramp shape if the input signal seeks to drive the output power level higher than can be achieved with the clamped supply voltage. This distortion increases adjacent channels spurious.
Furthermore, although a clamp voltage compatible with the minimum battery voltage ensures that the specifications may be met in all conditions, it limits the output power level for higher battery voltages. Thus, the supply voltage limitation at the minimum clamp voltage results in the dynamic range of the supply voltage Vcc and thereby the output power of the power amplifier circuit 101 being substantially reduced.
Also, a clamping voltage will result in a substantial voltage drop over the FET 103 at higher battery voltages where the output power may be limited by the clamp voltage rather than the battery voltage. Since the supply current for the power amplifier flows through the FET 103, the power dissipation of the FET 103 becomes substantial thereby reducing efficiency of the power amplifier, increasing battery drain and increasing heat dissipation in the FET 103.
For example, a typical battery voltage may vary between 2.8 V and 5.5 V. If the supply voltage Vcc is clamped at e.g. 2.5 V, the dynamic range of Vcc is limited to between 0 and 2.5V even with a battery voltage of 5.5V. Furthermore, at a battery voltage of 5.5V the voltage drop over the FET 103 is 3 V for a Vcc of 2.5V. Thus, more power is dissipated in the FET 103 than in the power amplifier. The reduced dynamic range may accordingly not only reduce the output power level of the power amplifier circuit but may also increase the heat dissipation as the power which is not transmitted is dissipated in the FET 103.
Hence, an improved power amplifier module would be advantageous and in particular a power amplifier module which is practical to implement and/or allows increased flexibility, increased dynamic range of the output power, reduced heat dissipation, improved transient performance, reduced adjacent channels spurious and/or increased battery life would be advantageous. In particular a power amplifier module suitable for a TDMA communication system and providing improved output power control and/or increased coverage would be advantageous.